The invention relates to a semiconductor device having a low resistive contact, and more particularly to a bipolar transistor having a low resistive collector plug.
A high speed silicon bipolar transistor with a small size is attractive. The realization of a high speed performance of the silicon bipolar transistor depends upon many factors, one of which is its collector series resistance. The reduction of the collector series resistance of the bipolar transistor makes it possible to accomplish the high speed performance thereof.
The conventional silicon bipolar transistor having a reduced collector resistance will be described with reference to FIG. 1. In FIG. 1, the conventional silicon bipolar transistor has a p-type silicon substrate 1. An n.sup.+ -type low resistive buried layer 2 is formed on the silicon substrate 1. The n.sup.+ -type low resistive buried layer 2 is so doped with an n-type dopant that the resistivity of the low resistive buried layer 2 is reduced. An n-type silicon epitaxial layer 3 is formed on the n.sup.+ -type low resistive buried layer 2. The n-type silicon epitaxial layer 3 is doped with an n-type dopant up to a lower dopant concentration of approximately 10.sup.16 cm.sup.-3 than a dopant concentration of the n.sup.+ -type low resistive buried layer 2. Trench grooves are formed in the n-type silicon epitaxial layer 3 and the n.sup.+ -type low resistive buried layer 2 so that a bottom of each of the trench grooves reaches the p-type silicon substrate 1 through the above two layers 2 and 3. The trench grooves are filled with a dielectric or an insulation material so that trench isolation regions 12 are formed in the n-type silicon epitaxial layer 3 and the n.sup.+ -type low resistive buried layer 2. The trench isolation regions serve to electrically separate a bipolar transistor from other elements.
Further, an insulation film 8 is formed on the n-type silicon epitaxial layer 3. Portions of the insulation film 8 are so removed by etching that openings are formed in the insulation film 8. An ion-implantation of a p-type dopant into the n-type silicon epitaxial layer 3 is accomplished through one of the openings formed in the insulator film 8 followed by a diffusion of the p-type dopant so that a p-type base region 6 is formed at an upper portion of the n-type silicon epitaxial layer 3. Subsequently, an ion-implantation of an n-type dopant into the p-type base region 6 is accomplished through another of the openings formed in the insulator film 8 followed by a diffusion of the n-type dopant so that an n-type emitter region 7 is formed at an upper portion of the p-type base region 6.
In addition, an ion-implantation of the n-type dopant into the n-type silicon epitaxial layer 3 is accomplished through another of the openings formed in the insulator film 8 followed by a diffusion of the n-type dopant so that an n-type low resistive diffusion region 16. The n-type low resistive diffusion region 16 is so formed that its bottom reaches at least on the n.sup.+ -type low resistive buried layer 2. The n-type low resistive diffusion region 16 also serves as a collector plug of the bipolar transistor. Since the n-type low resistive diffusion region 16 has a high dopant concentration and a low resistivity, the collector series resistance is reduced. Namely, the existence of the n-type low resistive diffusion region 16 makes the collector series resistance reduced. The reduction of the collector series resistance provided by the n-type low resistive diffusion region 16 permits the bipolar transistor to exhibit a high speed performance. Phosphorus is available as the above n-type dopant, although other dopants such as arsenic are also available.
Subsequently, an evaporation of aluminium or an aluminium based metal suitable as a contact material is so implemented that the contact material layer not only covers the surface of the device, but also contacts with the p-type base region 6, the n-type emitter region 7 and the n-type low resistive diffusion region 16 respectively. After that, the contact material layer is so etched that portions of the contact material layer remain but only in the vicinity of the above opening portions. Namely, portions of the contact material layer remain at the openings of the insulation film 8 over the p-type base region 6, the n-type emitter region 7 and the n-type low resistive diffusion region 16 respectively so that the respective remaining portions of the contact material layer serve as a base contact 11, an emitter contact 10 and a collector contact 9.
The conventional bipolar transistor having the n-type low resistive diffusion region 16, however, has disadvantages in a high integration for integrated circuits, which will be described.
As described above, the formation of the n-type low resistive diffusion region 16 requires a diffusion process. Thus, in the diffusion process, the n-type dopant is diffused not only in the vertical direction relative to the surface of the p-type silicon substrate 1 but also in the lateral direction and thus the parallel direction relative to the surface of the p-type silicon substrate 1. The diffusion of the n-type dopant in the lateral direction provides a possibility of a contact of the n-type low resistive diffusion region 16 with the p-type base region 6. Even if this does not happen, the diffusion of the n-type dopant in the lateral direction makes the n-type low resistive diffusion region 16 approach the p-type base region 6. Accordingly, it is necessary to separate the n-type low resistive diffusion region 16 from the p-type base region 6 in order to keep them from being in contact with one another. Alternatively, it is necessary to isolate by an insulation film the n-type low resistive diffusion region 16 from the p-type base region 6. This makes it difficult to improve the miniaturization of the bipolar transistor. This further makes it difficult to achieve a high density integration of integrated circuits.
Another conventional silicon bipolar transistor having a reduced collector resistance will be described with reference to FIG. 2. The structure of this other silicon bipolar transistor is analogous to the structure of the above mentioned silicon bipolar transistor as illustrated in FIG. 1, except for the n-type low resistive diffusion region 16. In FIG. 2, this other conventional silicon bipolar transistor has a p-type silicon substrate 1. An n.sup.+ -type low resistive buried layer 2 is formed on the silicon substrate 1. The n.sup.+ -type low resistive buried layer 2 is so doped with an n-type dopant that the resistivity of the buried layer 2 is reduced. An n-type silicon epitaxial layer 3 is formed on the n.sup.+ -type low resistive buried layer 2. The n-type silicon epitaxial layer 3 is doped with an n-type dopant up to a lower dopant concentration of approximately 10.sup.16 cm.sup.-3 than a dopant concentration of the n.sup.+ -type low resistive buried layer 2. Trench grooves are formed in the n-type silicon epitaxial layer 3 and the n.sup.+ -type low resistive buried layer 2 so that a bottom of each of the trench grooves reaches the p-type silicon substrate 1 through the above two layers 2 and 3. The trench grooves are filled with a dielectric or an insulation material so that trench isolation regions 12 are formed in the n-type silicon epitaxial layer 3 and the n.sup.+ -type low resistive buried layer 2. The trench isolation regions serve to electrically separate a bipolar transistor from other elements.
Further, an insulation film 8 is formed on the n-type silicon epitaxial layer 3. Portions of the insulation film 8 are removed by etching so that openings are formed in the insulation film 8. An ion-implantation of a p-type dopant into the n-type silicon epitaxial layer 3 is accomplished through one of the openings formed in the insulator film 8 followed by a diffusion of the p-type dopant so that a p-type base region 6 is formed at an upper portion of the n-type silicon epitaxial layer 3. Subsequently, an ion-implantation of an n-type dopant into the p-type base region 6 is accomplished through another of the openings formed in the insulator film 8 followed by a diffusion of the n-type dopant so that an n-type emitter region 7 is formed at an upper portion of the p-type base region 6.
In addition, a trench groove is formed in the n-type silicon epitaxial layer 3 and the n.sup.+ -type low resistive buried layer 2 so that a bottom of the trench groove does not reach the p-type silicon substrate 1 and thus exists within the n.sup.+ -type low resistive buried layer 2. The trench groove is filled with a metal such as tungsten so that a buried metal region 4 is formed in the n-type silicon epitaxial layer 3 and the n.sup.+ -type low resistive buried layer 2. The buried metal region 4 serves as a collector plug of the bipolar transistor. Since the buried metal region 4 has a lower resistivity than the resistivity of the above n-type low resistive diffusion region 16 as illustrated in FIG. 1, the collector series resistance is much more reduced. Namely, the existence of the buried metal region 4 makes the collector series resistance reduced. The reduction of the collector series resistance provided by the buried metal region 4 permits the bipolar transistor to exhibit high speed performance.
Subsequently, vapor deposition of aluminium or an aluminium based metal suitable as a contact material is so implemented that the contact material layer covers the surface of the device, but contacts the p-type base region 6, the n-type emitter region 7 and the buried metal region 4 respectively. After that, the contact material layer is so etched that portions of the contact material layer remain only in the vicinity of the above opening portions. Namely, portions of the contact material layer remain at the openings in the insulation film 8 over the p-type base region 6, the n-type emitter region 7 and the buried metal region 4 respectively so that the respective remaining portions of the contact material layer serve as a base contact 11, an emitter contact 10 and a collector contact 9.
The conventional bipolar transistor having the buried metal region 4, however, has disadvantages in high density integration for integrated circuits, which will be described.
An interface between the buried metal region 4 and the n-type silicon eqitaxial layer 3 or the n.sup.+ -type low resistive buried layer 2 exhibits a Schottky junction as a metal-semiconductor junction. The Schottky junction forms a Schottky barrier. Since the n-type silicon epitaxial layer 3 has the dopant concentration of approximately 10.sup.16 cm.sup.-3 as described above, electrons are able to move from the n-type silicon epitaxial layer 3 to the buried metal region 4 through the Schottky junction, or carriers are able to move from the buried metal region 4 to the n-type silicon epitaxial layer 3. This causes an electrical current of carriers to flow from the buried metal region 4 to the n-type silicon epitaxial layer 3 in the lateral direction. Namely, a current flow occurs. Accordingly, this other bipolar transistor having the buried metal region 4 is required to keep the electrical current of carriers in the lateral direction from reaching the p-type base region 6. Thus, it is necessary to prevent a short circuit current from the buried metal region 4 to the p-type base region through the n-type silicon epitaxial layer 3. This requires the buried metal region 4 to be a predetermined distance from the n-type silicon epitaxial layer 3. This makes it difficult to achieve the minimization of the device size, and further keeps a high density integration of integrated circuits from being achieved.
Accordingly, the development of a novel bipolar transistor having a lower collector series resistance is desired to achieve not only high speed performance of the bipolar transistor provided by making the collector series resistance reduced but also an improvement in the miniaturization of the device size and thus an improvement in the high integration of the circuits. Further, the development of a novel metal and semiconductor contact structure breaking a Schottky barrier to prevent carriers from moving across an interface of metal and semiconductor regions is needed.